SH7065 Datasheet, PDF (631/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 15 A/D Converter
15.3 CPU Interface
The A/D data registers (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1) are 16-bit registers, but
they are connected to the CPU by an 8-bit data bus. Therefore, the upper and lower bytes of these
registers must be read separately.
To prevent the data being changed between the reads of the upper and lower bytes of an A/D data
register, the lower byte is read via a temporary register (TEMP). The upper byte can be read
directly.
Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte
value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When performing byte-size reads on an A/D data register, always read the upper byte before the
lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect
data may be obtained. If a word-size read is performed on an A/D data register, reading is
performed in upper byte, lower byte order automatically.
Figure 15.2 shows the data flow when reading an A/D data register.
Rev. 5.00 Sep 11, 2006 page 609 of 916
REJ09B0332-0500