SH7065 Datasheet, PDF (610/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
In Serial Data Transmit Operations
In transmission, when transmit data is written to the transmit FIFO by the CPU or DMAC and the
TE bit is set to 1 in the serial control register (SCSCR), the data is first transferred to the transmit
shift register (SCTSR) in the order of writing to the transmit FIFO, a parity bit is added by the
parity generator (P/G), and then serial data is transmitted from the TxD pin.
Each time data is written into the transmit FIFO, the value in bits T4 to T0 in the FIFO data count
register (SCFDR) is incremented, and each time data is transferred to SCTSR the value in bits T4
to T0 is decremented. The current number of data bytes in the transmit FIFO can thus be found by
reading bits T4 to T0 in SCFDR.
A value of H'10 in bits T4 to T0 means that data has been written into all 16 stages of the transmit
FIFO. If additional data is written to the FIFO in this state, bits T4 to T0 will not be incremented
and the written data will be lost.
When the transmit trigger number is set and transmit data is written to the FIFO by the DMAC, if
bit 17 (Flag Clear Timing Select (FCS)) in the DMAC’s DMA channel control register (CHCRn)
is 0 and bit 6 (DREQ Select (DS)) is 1, even though TDFE in serial status register 1 (SCISSR) is
cleared to 0 by execution of the DMAC transfer, the DMAC will continue to transfer data to the
FIFO until the value in the DMA transfer count register reaches 0. In this case, therefore, care
must be taken not to write data exceeding the number of empty bytes in SCFTDR indicated by the
FIFO control register (SCFCR) (see section 14.2.10, FIFO Control Register (SCFCR)).
In Serial Data Receive Operations
In reception, serial data input from the RxD pin is first captured in the receive shift register
(SCRSR) in the order specified by the RLM bit in the serial status 2 register (SC2SSR). A parity
bit check is carried out, and if there is a parity error the P (parity error) flag for that data is set to 1.
A stop bit check is also performed, and if a framing error is found the F (framing error) flag for
that data is set to 1. The receive FIFO buffer has a 10-bit configuration, with the P and F flags for
each 8-bit data unit stored together with that data.
Receive FIFO Control in Normal Operation: Receive data held in the receive FIFO buffer is
read by the CPU or DMAC.
Each time data is transferred from SCRSR to the receive FIFO, the value in bits R4 to R0 in
SCFDR is incremented, and each time the CPU or DMAC reads receive data from the receive
FIFO, the value in bits R4 to R0 is decremented. The current number of data bytes in the receive
FIFO can thus be found by reading bits R4 to R0 in SCFDR.
Rev. 5.00 Sep 11, 2006 page 588 of 916
REJ09B0332-0500