SH7065 Datasheet, PDF (130/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Frequency Control Register: The frequency control register contains control bits for on/off
control of the clock output from the CK/CKIO pin, and the frequency division ratios for the master
clock, peripheral clock, external bus clock, and clock output.
Standby Control Register: The standby control register contains power-down mode control bits.
4.1.3 CPG Pin Configuration
Table 4.1 shows the CPG pins and their functions.
Table 4.1 CPG Pins
Pin Name
Mode control pins
Abbreviation
MD5–MD3
I/O
Input
Crystal input/output pins XTAL
(clock input pins)
EXTAL
Output
Input
Clock input/output pin
CKIO
I/O
PLL capacitance
connection pins
CK
CAP1
CAP2
Output
Input
Input
Function
Set clock operating mode.
Connects crystal resonator.
Connects crystal resonator, or used as
external clock input pin.
Used as external clock input or external
clock output pin. In output mode, can be
fixed in high-impedance state.
Used as external clock output pin. Can be
fixed in high-impedance state.
Connects capacitance (recommended
value: 470 pF) for PLL circuit 1 operation.
Connects capacitance (recommended
value: 470 pF) for PLL circuit 2 operation.
4.1.4 CPG Register Configuration
Table 4.2 shows the CPG register configuration.
Table 4.2 CPG Register
Name
Frequency control
register
Abbreviation R/W
FRQCR
R/W
Initial Value
Depends on
clock mode
Address
Access Size
H'FFFF 1028 8, 16, 32
Rev. 5.00 Sep 11, 2006 page 108 of 916
REJ09B0332-0500