SH7065 Datasheet, PDF (591/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two cycles: an ID transmission cycle which specifies
the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate
between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving stations skip the data until data with a 1 multiprocessor bit is sent. When data with a
1 multiprocessor bit is received, each receiving stations compares that data with its own ID. The
station whose ID matches then receives the data sent next. Stations whose ID does not match
continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data
communication is carried out among a number of processors.
Figure 14.10 shows an example of inter-processor communication using a multiprocessor format.
Transmitting
station
Serial communication line
Receiving
station A
(ID = 01)
Receiving
station B
(ID = 02)
Receiving
station C
(ID = 03)
Receiving
station D
(ID = 04)
Serial
data
H'01
(MPB = 1)
H'AA
(MPB = 0)
ID transmission cycle:
Receiving station
specification
Data transmission cycle:
Data transmission
to receiving station
specified by ID
Legend:
MPB: Multiprocessor bit
Figure 14.10 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Rev. 5.00 Sep 11, 2006 page 569 of 916
REJ09B0332-0500