SH7065 Datasheet, PDF (270/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.3 Operation
8.3.1 Endian/Access Size and Data Alignment
The SH7065 supports both big-endian mode, in which the most significant byte (MSByte) is at the
0 address end in a string of byte data, and little-endian mode, in which the least significant byte
(LSByte) is at the 0 address end. The mode is set by means of the ENDIAN bit in area control
register 1 (ACR1_0 to ACR1_5).
A data bus width of 8, 16, or 32 bits can be selected for normal memory and DRAM. For
multiplexed I/O there is a choice of 8 or 16 bits. Data alignment is carried out according to the
data bus width and endian mode of each device. Thus, four read operations are needed to read
longword data from an 8-bit device. In the SH7065, data alignment and data length conversion
between the different interfaces is performed automatically.
The relationship between the endian mode, device data width, and access unit, is shown in tables
8.4 to 8.9. Instruction codes should be handled as word data. Similarly, with a 32-bit instruction
code, handle the A-field and B-field instruction codes as word data.
Table 8.4 32-Bit External Device/Big-Endian Access and Data Alignment
Data Bus
Operation
Address 0 byte access
Address 1 byte access
Address 2 byte access
Address 3 byte access
D31–
D24
Data
7–0
—
—
—
D23–
D16
—
Data
7–0
—
—
D15–
D8
—
—
Data
7–0
—
Address 0 word access Data Data —
15–8 7–0
Address 2 word access —
—
Data
15–8
Address 0 longword
access
Data Data Data
31–24 23–16 15–8
D7–
D0
—
—
—
Data
7–0
—
Data
7–0
Data
7–0
Strobe Signals
WRHH, WRHL, WRLH, WRLL,
HHBS, HLBS, LHBS, LLBS,
CASHH CASHL CASLH CASLL
Asserted
Asserted
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted Asserted Asserted
Rev. 5.00 Sep 11, 2006 page 248 of 916
REJ09B0332-0500