SH7065 Datasheet, PDF (576/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 5—IrDA Receive Data Inverse (RIVS): Allows inversion of the receive data polarity to be
selected in IrDA communication.
Bit 5: RIVS
Description
0
Receive data polarity inverted in reception
(Initial value)
1
Receive data polarity not inverted in reception
Note: Make the selection according to the characteristics of the IrDA modulation/demodulation
module.
Bits 4 to 0—Reserved: These bits are always read as 0 and should only be written with 0.
14.3 Operation
14.3.1 Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
An IrDA block is also provided, enabling infrared communication conforming to IrDA 1.0 to be
executed by connecting an infrared transmission/reception unit.
Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
Selection of asynchronous, synchronous, or IrDA mode and the transmission format is made by
means of the serial mode register (SCSMR) and IrDA mode register (SCIMR) as shown in table
14.8. The SCI clock source is determined by a combination of the C/A bit in SCSMR, the IRMOD
bit in SCIMR, and the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in
table 14.9.
Rev. 5.00 Sep 11, 2006 page 554 of 916
REJ09B0332-0500