SH7065 Datasheet, PDF (261/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bits 8 to 5—DMA Single Address Mode Read Access Wait State Insertion Cycle
Specification (DDWR3 to DDWR0): These bits specify the number of wait states to be inserted
in reads from DRAM in DMA single address mode.
Bit 8:
DDWR3
Bit 7:
DDWR2
Bit 6:
DDWR1
Bit 5:
DDWR0
0
0
0
0
1
1
0
:
:
:
:
1
1
1
0
1
Note: Use the no wait setting for EDO DRAM.
Description
Normal Access
EDO Access
No waits
No waits
1 wait
Do not set
2 waits
Do not set
:
:
14 waits
Do not set
15 waits (Initial value) Do not set (Initial value)
Bit 4—Idle Cycle Insertion before Continuous Burst Operation in DMA Single Transfer in
RAS Down Mode (RDW): Specifies whether one idle cycle is to be inserted before burst
operation when the same DRAM row address is accessed in DMA single mode during RAS down
mode. This cycle is inserted only when access is switched from another space to the CS4 space or
CS5 space, or from read access to write access within the same CS4 or CS5 space.
Bit 4: RDW
0
1
Description
No idle cycle
1 idle cycle inserted
(Initial value)
Bit 3—Write Cycle CAS Assertion Width with Software Wait Setting (TCAS): Specifies the
CAS assertion width in a DRAM write cycle.
Bit 3: TCAS
Normal Access
0
1 cycle
(Initial value)
1
2 cycles
Note: Use the no wait setting for EDO DRAM.
Description
EDO Access
1 cycle
Do not set
(Initial value)
Bits 2 to 0—Reserved: These bits are always read as 0 and should only be written with 0.
Rev. 5.00 Sep 11, 2006 page 239 of 916
REJ09B0332-0500