SH7065 Datasheet, PDF (904/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Appendix C I/O Port Block Diagrams
Bus
released
PDR
RES
Internal
data bus
PDnDR
Modes 2/3
PDW
Dout
Dn
TIOC1A,
TIOC1B,
TIOC2A
Single-chip mode
PFC
PDnMD0
PDnMD1
Din
Standby
PDnIOR
SBYCR
HIZ
Legend:
PDR: Port D read signal
PDW: Port D write signal
RES: Reset signal
Dout: Data bus output timing signal
Din: Data bus input timing signal
TPU
TIOC1A,
TIOC1B,
TIOC2A
Note: n = 8 to 10
Figure C.21 PD8/D8/TIOC1A, PD9/D9/TIOC1B, PD10/D10/TIOC2A Block Diagram
(for Mask ROM version)
Rev. 5.00 Sep 11, 2006 page 882 of 916
REJ09B0332-0500