SH7065 Datasheet, PDF (579/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Table 14.9 SCSMR and SCSCR Settings for SCI Clock Source Selection
SCSMR
Bit 7:
C/A
0
1
SCSCR Setting
Bit 1: Bit 0:
CKE1 CKE0 Mode
0
0
Asynchronous
1
mode
1
0
1
0
0
Synchronous
1
mode
1
0
1
SCI Transmit/Receive Clock
Clock
Source SCK Pin Function
Internal SCI does not use SCK pin
Outputs clock with frequency of
16/8/4 times bit rate
External Inputs clock with frequency of 16/8/4
times bit rate
Internal Outputs serial clock
External Inputs serial clock
14.3.2 Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a 16-stage FIFO buffer structure,
so that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 14.3 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCI monitors the line, and when it goes to the space state (low level), recognizes
a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (LSB-first
or MSB-first order selectable), a parity bit (high or low level), and finally one or two stop bits
(high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the eighth, fourth, or second pulse of a clock with a
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