SH7065 Datasheet, PDF (297/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
EDO Mode
With DRAM, in addition to the mode in which data is output to the data bus only while the CAS
signal is asserted in a data read cycle, an EDO mode is also provided in which, once the CAS
signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is
output to the data bus until the CAS signal is next asserted. Either normal access/burst access
using fast page mode, or EDO mode normal access/burst access, can be selected for DRAM with
the EDO bit in DCR3. EDO mode normal access is shown in figure 8.22, and burst access in
figure 8.23. In burst access, only one-cycle access is possible only when column addresses are
consecutive. No-wait access must be used for EDO DRAM. No-wait access must be used for EDO
DRAM, and wait state insertion by means of the WAIT pin must not be used.
Rev. 5.00 Sep 11, 2006 page 275 of 916
REJ09B0332-0500