SH7065 Datasheet, PDF (334/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 32-bit readable/writable
registers that specify the transfer count for the channel (number of bytes, words, or longwords).
Setting H'00000001 gives a transfer count of 1, while H'00000000 gives the maximum setting of
4,294,967,296 (4G) transfers. During DMAC operation, the remaining number of transfers is
shown.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
Rev. 5.00 Sep 11, 2006 page 312 of 916
REJ09B0332-0500