SH7065 Datasheet, PDF (250/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.2 Register Descriptions
8.2.1 Bus Control Register (BCR)
The bus control register (BCR) is a 16-bit readable/writable register that specifies bus settings
common to all areas.
BCR is initialized to H'0000 by a power-on reset, but is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
BRQE BAS HIZCNT —
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit 15—BREQ Enable (BRQE): Enables or disables acceptance of the bus release request
(BREQ).
Bit 15: BRQE
0
1
Description
Bus release request (BREQ) is not accepted
Bus release request (BREQ) is accepted
(Initial value)
Bit 14—Byte Access Specification (BAS): Specifies the byte access control signals.
Bit 14: BAS
0
1
Description
Access by WRHH, WRHL, WRLH, and WRLL signals
Access by WR, HHBS, HLBS, LHBS, and LLBS signals
(Initial value)
Rev. 5.00 Sep 11, 2006 page 228 of 916
REJ09B0332-0500