SH7065 Datasheet, PDF (811/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 21 XRAM and YRAM
Section 21 XRAM and YRAM
21.1 Overview
The SH7065 has 4 kbytes each of XRAM and YRAM. The XRAM and YRAM are connected to
the CPU and DSP by a 16-bit X-bus and Y-bus, respectively, (figures 21.1 and 21.2), allowing 16-
bit-wide data exchange with the CPU and DSP. The XRAM and YRAM are also connected to the
CPU by a 32-bit-wide internal data bus (CDB) and to the direct memory access controller
(DMAC) by a 32-bit internal data bus (IDB) (figures 21.1 and 21.2), allowing 8-, 16-, or 32-bit-
wide access to the XRAM and YRAM.
The XRAM and YRAM can be accessed in parallel using the X-bus and Y-bus, enabling two data
transfer instructions to be executed simultaneously. XRAM and YRAM data can always be
accessed in one state, making this memory suitable for use in areas requiring high-speed access.
The contents of XRAM and YRAM are retained in sleep mode and standby mode.
The XRAM and YRAM are allocated to addresses H'FFFF8000 to H'FFFF8FFF and H'FFFFA000
to H'FFFFAFFF, respectively.
Internal data bus (CDB) (32 bits)
Internal data bus (IDB) (32 bits)
H'FFFF8000
H'FFFF8004
H'FFFF8001
H'FFFF8005
H'FFFF8002
H'FFFF8006
H'FFFF8003
H'FFFF8007
XRAM
H'FFFF8FFC
H'FFFF8FFD
H'FFFF8FFE
H'FFFF8FFF
X data bus (16 bits)
Figure 21.1 Block Diagram of XRAM
Rev. 5.00 Sep 11, 2006 page 789 of 916
REJ09B0332-0500