SH7065 Datasheet, PDF (317/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.4 Number of Access Cycles (SH7065A)
External Memory and External I/O
Table 8.11 shows the number of external access cycles for Mφ:CKE division ratios of 1:1, 1:1/2,
and 1:1/4. The CPU regards an external space write as being executed in one cycle, and performs
the next processing. However, the write actually takes the number of cycles shown in table 8.11.
Therefore, execution of an on-chip register or external access following an external space write by
the CPU is delayed until the end of the external space write.
Table 8.12 shows the number of idle cycles. For the number of accesses on a CKE basis, add this
number of idle cycles to the number of external bus idle cycles.
Table 8.11 Number of External Access Cycles (Mφ Basis)
Bus Master
Mφ:CKE
Division Ratio
Read/Write
Cycles in Access
from CPU
Cycles in Access
from DMAC
1:1
Read
Number of external bus
Number of external bus
cycles + 3
cycles + 1
Write
Number of external bus
cycles + 4
Number of external bus
cycles + 2
1:1/2
Read
Write
(Number of external bus
cycles) × 2 + (4 or 5)^*
(Number of external bus
cycles) × 2 + (6 or 7)^*
(Number of external bus
cycles) × 2 + (2 or 3)^*
(Number of external bus
cycles) × 2 + (4 or 5)^*
1:1/4
Read
(Number of external bus
cycles) × 4 + (5 to 8)^*
(Number of external bus
cycles) × 4 + (3 to 6)^*
Write
(Number of external bus
cycles) × 4 + (9 to 12)^*
(Number of external bus
cycles) × 4 + (7 to 10)^*
Note: * Depends on the phase difference between Mφ and CKE due to frequency division.
Rev. 5.00 Sep 11, 2006 page 295 of 916
REJ09B0332-0500