SH7065 Datasheet, PDF (482/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Bits 1 and 0—Mode 1 and 0 (MD1, MD0): These bits set the timer operating mode.
Bit 1: MD1
0
1
Bit 0: MD0
0
1
0
1
Description
Operation halted
(Initial value)
Operating mode 1 (transfer at crest)
Operating mode 2 (transfer at trough)
Operating mode 3 (transfer at crest and trough)
11.2.2 Timer Control Register (TCNR)
The timer control register (TCNR) is an 8-bit readable/writable register that controls enabling or
disabling of interrupt requests, selects enabling or disabling of register access, selects counter
operation or halting, and controls enabling or disabling of toggle output synchronized with the
PWM period.
TCNR is initialized to H'00 by a power-on reset and in standby mode. It is not initialized in
module standby mode.
Bit: 7
6
5
4
3
2
1
0
TTGE CST RPRO
—
—
—
TGIEN TGIEM
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
—
—
—
R/W
R/W
Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D
conversion start requests by a compare match between TCNT and the TPDR register, and by a
compare match between TCNT and 2Td (Td: dead time).
Bit 7: TTGE
0
1
Description
A/D conversion start request generation disabled
A/D conversion start request generation enabled
(Initial value)
The A/D conversion start timing in each operating mode is shown in table 11.3.
Rev. 5.00 Sep 11, 2006 page 460 of 916
REJ09B0332-0500