SH7065 Datasheet, PDF (627/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.2 Register Descriptions
Section 15 A/D Converter
15.2.1 A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)
Bit: 15
14
13
12
11
10
9
8
ADDRn AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
ADDRn AD1
AD0
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Note: n = A to D
The A/D data registers (ADDR) are 16-bit read-only registers that store the results of A/D
conversion. There are eight registers, ADDRA0 to ADDRD0, ADDRA1 to ADDRD1.
The result of A/D conversion is 10-bit data which is transferred to and stored in the ADDR
register for the selected channel. The upper 8 bits of the converted data correspond to the upper
byte of ADDR, and the lower 2 bits correspond to the lower byte. Bits 5 to 0 of the lower byte of
ADDR are reserved, and are always read as 0. Table 15.3 shows the correspondence between the
analog input channels and the A/D data registers.
The ADDR registers can be read by the CPU at all times. The upper byte is read directly, but the
lower byte data is transferred via a temporary register (TEMP). For details, see section 15.3, CPU
Interface.
The ADDR registers are initialized to H'0000 by a power-on reset and in standby mode.
Rev. 5.00 Sep 11, 2006 page 605 of 916
REJ09B0332-0500