SH7065 Datasheet, PDF (441/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation
When TGR is an output compare register: Figure 10.19 shows an operation example in which
PWM mode 1 has been designated for channel 0, and buffer operation has been designated for
TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1
output at compare match A, and 0 output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT value
TGR0B
TGR0A
H'0000
H'0200
H'0450
TGR0C H'0200
Transfer
TGR0A
H'0450
H'0200
H'0520
H'0450
H'0520
Time
TIOCA
Figure 10.19 Example of Buffer Operation (1)
Rev. 5.00 Sep 11, 2006 page 419 of 916
REJ09B0332-0500