SH7065 Datasheet, PDF (260/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bits 15 to 13—Idle Cycles after DRAM Access (DIW2 to DIW0): These bits specify the
number of idle cycles to be inserted between bus cycles when access is switched from the CS4 or
CS5 space to another space, or from read access to write access within the same CS4 or CS5
space. When switching to access to a different space, one idle cycle is inserted automatically in the
case of a read cycle, and two idle cycles in the case of a write cycle, even if “No idle cycles” is set.
When switching from a read cycle to a write cycle within the same space, two idle cycles are
inserted automatically.
Bit 15: DIW2
0
:
1
Bit 14: DIW1
0
1
:
1
Bit 13: DIW0
0
1
0
:
0
1
Description
No idle cycles
1 idle cycle inserted
2 idle cycles inserted
:
6 idle cycles inserted
7 idle cycles inserted
(Initial value)
Bits 12 to 9—DMA Single Address Mode Write Access Wait State Insertion Cycle
Specification (DDWW3 to DDWW0): These bits specify the number of wait states to be inserted
in writes to DRAM in DMA single address mode.
Bit 12:
Bit 11:
Bit 10:
Bit 9:
DDWW3 DDWW2 DDWW1 DDWW0
0
0
0
0
1
1
0
:
:
:
:
1
1
1
0
1
Note: Use the no wait setting for EDO DRAM.
Description
Normal Access
EDO Access
No waits
No waits
1 wait
Do not set
2 waits
Do not set
:
:
14 waits
Do not set
15 waits (Initial value) Do not set (Initial value)
Rev. 5.00 Sep 11, 2006 page 238 of 916
REJ09B0332-0500