SH7065 Datasheet, PDF (874/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Appendix B Pin States
Pin Function
Pin State
Type
I/O ports
Pin Name
PAn
PBn
PCn
PDn
Reset
State
Z
Z
Z
Z
Power-Down State
Software Hardware
Standby Standby Sleep
K^*4
Z
K
K^*4
Z
K
K^*4
Z
K
K^*4
Z
K
Bus-
Released
State
Software
Standby
in Bus-
Released
State
Hardware
Standby
in Bus-
Released
State
I/O
K^*4
Z
I/O
K^*4
Z
I/O
K^*4
Z
I/O
K^*4
Z
PE23–PE21,
Z
PE19–PE17
PEn other than
Z
above
PFn
Z
PGn
Z
PHn
Z
Z
Z
K^*4
Z
K^*4
Z
K^*4
Z
K^*4
Z
K
I/O
Z
Z
K
I/O
K^*4
Z
K
I/O
K^*4
Z
K
I/O
K^*4
Z
K
I/O
K^*4
Z
PIn
Z
Z
Z
I
I
Z
Z
Legend:
I: Input
O: Output
H: High-level output
L: Low-level output
Z: High-impedance state
K: Input pins are in the high-impedance state; output pins maintain their previous state.
Notes: 1. Depends on the clock mode.
2. Z or O depending on frequency control register (FRQCR) setting.
3. Z or O depending on bus control register (BCR) setting.
4. Z or O depending on standby control register (SBYCR) setting.
5. Z in on-chip ROM enabled modes and single-chip mode.
6. Z for all pins when PUOA, PVOA, PWOA, PUOB, PVOB, and PWOB are multiplexed.
Rev. 5.00 Sep 11, 2006 page 852 of 916
REJ09B0332-0500