SH7065 Datasheet, PDF (551/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5: TE
Description
0
Transmission disabled^*1
(Initial value)
1
Transmission enabled^*2
Notes: 1. The TDFE flag in SC1SSR is not affected by clearing TE to 0, and the TxD pin is fixed
high.
2. Serial transmission is started when transmit data is written to SCFTDR in this state.
Serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit
is set to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4: RE
Description
0
Reception disabled^*1
(Initial value)
1
Reception enabled^*2
Notes: 1. Clearing the RE bit to 0 does not affect the RDF, FER, PER, ORER, DR, and BRK
flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. When a setting is made to
output a serial clock in synchronous mode, if TE = 0, the serial clock is output and
reception is started as soon as RE is set to 1.
When TE = 1 and RE = 1, serial data is received simultaneously with the transmit
operation.
SCSMR setting must be made to decide the reception format before setting the RE bit
to 1.
Rev. 5.00 Sep 11, 2006 page 529 of 916
REJ09B0332-0500