SH7065 Datasheet, PDF (315/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
8.3.7 Bus Arbitration
When the bus release request signal (BREQ) is asserted in accordance with the setting of the
BRQE bit in BCR, the SH7065 releases the bus as soon as the currently executing bus cycle ends,
and outputs the bus request acknowledge signal (BACK). However, bus release is not performed
between a read cycle and write cycle during execution of a TAS instruction (unless the destination
of TAS instruction execution is on-chip RAM). Also, bus arbitration is not performed between bus
cycles generated due to the fact that the data bus width is smaller than the access size, such as
when a longword access is made to 8-bit memory. When BREQ is negated, BACK is negated and
use of the bus is resumed. See Appendix B.1, Pin States in Reset, Power-Down State, and Bus-
Released State, for the pin states when the bus is released.
Sometimes, the SH7065 may want to take back the bus while in the process of releasing it. This
happens if a memory refresh request is generated internally, or an interrupt is requested, and the
relevant processing must be executed. For this reason, the SH7065 is provided with an IRQOUT
pin to output a bus request signal. If the SH7065 needs to take back the bus, it asserts the IRQOUT
signal. On receiving this IRQOUT signal assertion, the device that asserted the external bus
request negates the BREQ signal in order to release the bus. The bus is thereby returned to the
SH7065, which then carries out the necessary processing. Note that if the device that asserted the
external bus request does not return the bus within the time specified as the DRAM refresh
interval, the SH7065 will not be able to carry out refreshing, and RAM contents may be lost.
There are two cases in which the IRQOUT pin is asserted: (1) when a memory refresh request has
been issued and the refresh cycle has not yet begun, and (2) when an interrupt source occurs and
the interrupt request level is higher than that set in the interrupt mask bits (I3 to I0) in the status
register (SR).
The SH7065 has two internal bus masters: the CPU and the DMAC. When DRAM is connected
and refresh control is performed, refresh requests constitute a third bus master. In addition to these
are bus requests from external devices. If requests occur simultaneously, priority is given, in high-
to-low order, to a refresh request, a bus request from an external device, the DMAC, and the CPU.
If an external space access request by the CPU or DMAC and a bus request by an external device
occur, in that order, during execution of a refresh cycle, acceptance of the bus request by the
external device will be delayed until the refresh cycle and external space access have been
executed. Similarly, if an external space access request by the CPU or DMAC and a refresh
request occur, in that order, execution of the refresh cycle after the SH7065 acquires the bus will
be delayed until the external space access has been executed.
Bus requests from off-chip are not accepted in sleep mode.
If BREQ is asserted in sleep mode and the DMAC is subsequently activated, external access by
the DMAC is delayed until BREQ is negated.
Rev. 5.00 Sep 11, 2006 page 293 of 916
REJ09B0332-0500