SH7065 Datasheet, PDF (333/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

9.2 Register Descriptions
Section 9 Direct Memory Access Controller (DMAC)
9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3)
Bit: 31 30 29 28 27 26 25 24 23
0
............................
Initial value: — — — — — — — — — ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} R/W
DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a count function, and during a
DMA transfer they indicate the next source address. In single address mode, the SAR value is
ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit
transfer. Operation cannot be guaranteed if a different address is set.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
9.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)
Bit: 31 30 29 28 27 26 25 24 23
0
............................
Initial value: — — — — — — — — — ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . .} R/W
DMA destination address registers 0 to 3 (DAR0 to DAR3) are 32-bit readable/writable registers
that specify the destination address of a DMA transfer. These registers have a count function, and
during a DMA transfer they indicate the next destination address. In single address mode, the
DAR value is ignored when a device with DACK has been specified as the transfer destination.
Specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit
transfer. Operation cannot be guaranteed if a different address is set.
The value of these registers is undefined after a power-on reset, and in hardware standby mode
and software standby mode.
Rev. 5.00 Sep 11, 2006 page 311 of 916
REJ09B0332-0500