SH7065 Datasheet, PDF (233/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.3 Operation
Section 7 User Break Controller (UBC)
7.3.1 User Break Operation Sequence
The sequence of operations from setting of break conditions to user break interrupt exception
handling is described below.
1. As break conditions, set the user break address in the user break address register (UBAR), the
address bits to be masked in the user break address mask register (UBAMR), and the type of
bus cycle on which a break is to be executed in the user break bus cycle register (UBBR). If
any pair of bits from among the CPU cycle/DMA cycle select bits (CP1, CP0), instruction
fetch/data access select bits (ID1, ID0), or read/write select bits (RW1, RW0) in UBBR is set
to 00 (user break interrupt not generated), a user break interrupt will not be generated even if
other conditions are satisfied. If the user break interrupt is to be used, a condition must be set
in all of these bit pairs.
2. If the user break interrupt enable bit (UBIE) in the user break bus cycle register (UBBR) is set
to 1 when a break condition occurs, the UBC sends a user break interrupt request signal to the
interrupt controller (INTC).
3. When the INTC receives the user break interrupt request signal, it determines its priority. As
the priority level of the user break interrupt is 15, it is accepted if the level set in the interrupt
mask bits (I3 to I0) in the status register (SR) is 14 or less. If the level set in bits I3 to I0 is 15,
the user break interrupt is not accepted, but is held pending until it can be. As the setting of bits
I3 to I0 is 15 during NMI exception handling, a user break interrupt is not accepted during
execution of the NMI exception service routine. However, changing the setting of bits I3 to I0
to level 14 or below at the start of the NMI exception service routine will enable subsequent
user break interrupts to be accepted. For details of priority determination, see section 6,
Interrupt Controller (INTC).
4. The INTC sends a user break interrupt request signal to the CPU. On receiving this signal, the
CPU begins user break interrupt exception handling. For details of interrupt exception
handling, see section 5, Exception Handling, and section 6.4, Operation.
Rev. 5.00 Sep 11, 2006 page 211 of 916
REJ09B0332-0500