SH7065 Datasheet, PDF (284/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
SH7065F Bus Timing
Timing waveforms when longword access is performed to external word-size memory space are
shown in figure 8.11. The SH7065F performs external accesses consecutively. The CS signal is
asserted during this time, and remains asserted.
CKE
A25–A2
A1
CSn
WR
Read RD
D15–D0
WR
Write WRxx
D15–D0
BS
T1
T2
T1
T2
t_AD
t_AD
t_AD
t_CSD1
t_WSD2
t_RSD1 t_OE t_RSD2
t_RDS
t_ACC
t_RDH
t_WSD1
t_CSD2
t_WSD1
t_RSD1 t_OE t_RSD2
t_RDS
t_ACC
t_RDH
t_WSD2
t_AS
t_WSD1
t_WDD
t_WSD2 t_WR t_AS
t_WRH t_WSD1
t_{WDD(min=tWDH)}
t_WSD2 t_WR
t_WRH
t_WDH
t_BSD1
t_BSD2
t_BSD1
t_BSD2
Figure 8.11 SH7065F Bus Timing
Rev. 5.00 Sep 11, 2006 page 262 of 916
REJ09B0332-0500