SH7065 Datasheet, PDF (20/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.5.1 Register Configuration ......................................................................................... 712
18.5.2 Port D Data Register H (PDDRH) ....................................................................... 712
18.5.3 Port D Data Register L (PDDRL) ........................................................................ 713
18.6 Port E ................................................................................................................................ 714
18.6.1 Register Configuration ......................................................................................... 715
18.6.2 Port E Data Register H (PEDRH) ........................................................................ 715
18.6.3 Port E Data Register L (PEDRL) ......................................................................... 716
18.7 Port F................................................................................................................................. 717
18.7.1 Register Configuration ......................................................................................... 717
18.7.2 Port F Data Register L (PFDRL) ......................................................................... 718
18.8 Port G................................................................................................................................ 719
18.8.1 Register Configuration ......................................................................................... 719
18.8.2 Port G Data Register H (PGDRH) ....................................................................... 719
18.9 Port H................................................................................................................................ 721
18.9.1 Register Configuration ......................................................................................... 721
18.9.2 Port H Data Register (PHDR) .............................................................................. 721
18.10 Port I ................................................................................................................................. 723
18.10.1 Register Configuration ......................................................................................... 723
18.10.2 Port I Data Register (PIDR) ................................................................................. 724
Section 19 256 kB Flash Memory (F-ZTAT).............................................................. 725
19.1 Features ............................................................................................................................. 725
19.2 Overview........................................................................................................................... 726
19.2.1 Block Diagram ..................................................................................................... 726
19.2.2 Mode Transitions ................................................................................................. 727
19.2.3 On-Board Programming Modes ........................................................................... 728
19.2.4 Flash Memory Emulation in RAM....................................................................... 730
19.2.5 Differences between Boot Mode and User Program Mode.................................. 731
19.2.6 Block Configuration............................................................................................. 732
19.3 Pin Configuration .............................................................................................................. 733
19.4 Register Configuration ...................................................................................................... 734
19.5 Register Descriptions ........................................................................................................ 735
19.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 735
19.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 738
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 739
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 739
19.5.5 RAM Emulation Register (RAMER) ................................................................... 740
19.6 On-Board Programming Modes ........................................................................................ 742
19.6.1 Boot Mode ........................................................................................................... 743
19.6.2 User Program Mode............................................................................................. 747
19.7 Programming/Erasing Flash Memory................................................................................ 748
Rev. 5.00 Sep 11, 2006 page xx of xxii