SH7065 Datasheet, PDF (564/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
The bit rate error in asynchronous mode is found from the following equations:
Error (%) =
Pφ × 10⁶
(N + 1) × B × 64 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 16 times the bit rate)
Error (%) =
Pφ × 10⁶
(N + 1) × B × 32 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 8 times the bit rate)
Error (%) =
Pφ × 10⁶
(N + 1) × B × 16 × 2^{2n–1 – 1 × 100}
(When operating on a base clock of 4 times the bit rate)
Table 14.3 shows sample SCBRR settings in asynchronous mode, and table 14.4 shows sample
SCBRR settings in synchronous mode.
Rev. 5.00 Sep 11, 2006 page 542 of 916
REJ09B0332-0500