SH7065 Datasheet, PDF (60/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.5 DSP Instruction Destination Register Data Formats
Registers
Instructions
Guard Bits
Register Bits
39
32 31
16 15
0
A0, A1
DSP
operations
Fixed-point, PSHA,
PMULS
(Sign
40-bit result
extension)
Integer, PDMSB
(Sign
24-bit result Cleared to 0
extension)
Logical, PSHL
Cleared to 0 16-bit result Cleared to 0
Data transfer MOVS.W
Sign
extension
16-bit result Cleared to 0
MOVS.L
Sign
extension
32-bit data
A0G,
A1G
Data transfer MOVS.W
MOVS.L
Data
Data
Not updated
Not updated
X0, X1
Y0, Y1
M0, M1
DSP
operations
Fixed-point, PSHA,
PMULS
Integer, logical, PDMSB,
PSHL
32-bit result
16-bit result Cleared to 0
Data transfer MOVX.W, MOVY.W,
MOVS.W
16-bit data Cleared to 0
MOVS.L
32-bit data
Rev. 5.00 Sep 11, 2006 page 38 of 916
REJ09B0332-0500