SH7065 Datasheet, PDF (633/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 15 A/D Converter
15.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and multi mode. The operation in these two modes is described
below.
15.4.1 Single Mode (MULTI = 0)
Single mode should be selected for A/D conversion on only one channel. A/D conversion starts
when the ADST bit in the A/D control/status register (ADCSR) is set to 1 by software or external
trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared
to 0 when conversion ends.
When conversion ends, the ADF bit in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an
ADI interrupt is requested. To clear the ADF bit, first read ADF when set to 1, then write 0 to
ADF.
To prevent incorrect operation, A/D conversion should be halted by clearing the ADST bit to 0
before changing the mode or analog input channel. After the change is made, A/D conversion is
restarted by setting the ADST bit to 1 (the mode or channel change and setting of the ADST bit
can be carried out simultaneously).
An example of the operation when channel 1 (AN1) is selected and A/D conversion is performed
in single mode is described below. Figure 15.3 shows a timing diagram for this example (bit
specifications in the operation example refer to the ADCSR0 register).
1. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the
A/D interrupt request is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion ends, the result is transferred to ADDRB0. At the same time ADF is set
to 1, ADST is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt service routine is started.
5. The routine reads ADF set to 1, then writes 0 to ADF.
6. The routine reads and processes the conversion result (ADDRB0).
7. Execution of the A/D interrupt service routine ends. After this, if the ADST bit is set to 1, A/D
conversion starts again and steps (2) to (7) are repeated.
Rev. 5.00 Sep 11, 2006 page 611 of 916
REJ09B0332-0500