SH7065 Datasheet, PDF (47/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 2 CPU
Table 2.1 SR Register Bits
Bits
27–16
11
10
9
8
7–4
3, 2
1
0
31–28,
15–12
Name (Abbreviation)
Function
Repeat counter (RC)
These bits specify number of repeats in repeat (loop)
control (2 to 4095).
Y pointer modulo addressing 1: Modulo addressing mode is enabled for Y memory
specification (DMY)
address pointer Ay (R6, R7).
X pointer modulo addressing 1: Modulo addressing mode is enabled for X memory
specification (DMX)
address pointer Ax (R4, R5).
M bit
Used by DIV0S/U and DIV1 instructions.
Q bit
Interrupt request mask
(IMASK)
These bits show the interrupt request acceptance level
(0 to 15).
Repeat flags (RF1, RF0)
Used for zero-overhead repeat (loop) control.
Set as follows when the SETRC instruction is used.
1-step repeat: 00
2-step repeat: 01
3-step repeat: 11
4 or more steps:10
RE – RS = –4
RE – RS = –2
RE – RS = 0
RE – RS > 0
Saturation operation bit (S) Used with MAC and DSP instructions.
1: Specifies a saturation operation (preventing
overflow)
T bit
With MOVT, CMP/cond, TAS, TST, BT, BT/S, BF,
BF/S, SETT, CLRT, and DT instructions:
0: Indicates True
1: Indicates False
With ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC,
SHAR/L, SHLR/L, ROTR/L. and ROTCR/L
instructions:
1: Indicates occurrence of carry, borrow, overflow, or
underflow
0 bits
0: Always read as 0.
Only 0 should be written to these bits.
Rev. 5.00 Sep 11, 2006 page 25 of 916
REJ09B0332-0500