SH7065 Datasheet, PDF (480/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Name
Abbre-
Initial
viation R/W Value Address
Access Size
Timer general register VU
TGRVU R/W H'FFFF H'FFFF 04A2 16, 32
Timer general register WU
TGRWU R/W H'FFFF H'FFFF 04B2 16, 32
Timer general register U
TGRU
R/W H'FFFF H'FFFF 0494 16, 32
Timer general register V
TGRV
R/W H'FFFF H'FFFF 04A4 16, 32
Timer general register W
TGRW
R/W H'FFFF H'FFFF 04B4
16, 32
Timer general register UD
TGRUD R/W H'FFFF H'FFFF 0496 16, 32
Timer general register VD
TGRVD R/W H'FFFF H'FFFF 04A6 16, 32
Timer general register WD
TGRWD R/W H'FFFF H'FFFF 04B6 16, 32
Timer dead time counter 0
TDCNT0 R
H'0000 H'FFFF 0498 16, 32
Timer dead time counter 1
TDCNT1 R
H'0000 H'FFFF 049A 16, 32
Timer dead time counter 2
TDCNT2 R
H'0000 H'FFFF 04A8 16, 32
Timer dead time counter 3
TDCNT3 R
H'0000 H'FFFF 04AA 16, 32
Timer dead time counter 4
TDCNT4 R
H'0000 H'FFFF 04B8 16, 32
Timer dead time counter 5
TDCNT5 R
H'0000 H'FFFF 04BA 16, 32
Timer dead time data register TDDR
R/W H'FFFF H'FFFF 048C 16, 32
Timer period buffer register
TPBR
R/W H'FFFF H'FFFF 048A 16, 32
Timer period data register
TPDR
R/W H'FFFF H'FFFF 0488 16, 32
Note:
Registers TBRU to TBRW each have two addresses, a buffer operation address (shown
first) and a free operation address (shown second). A value written to the buffer operation
address is transferred to the corresponding TGR at the timing set in bits MD1 and MD0 in
the timer mode register (TMDR). A value set in the free operation address is transferred to
the corresponding TGR immediately.
Rev. 5.00 Sep 11, 2006 page 458 of 916
REJ09B0332-0500