SH7065 Datasheet, PDF (618/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
Sending a Break Signal
The TxD pin is a general I/O pin whose input/output direction and level are determined by the I/O
port data register (DR) and the control register (CR) of the pin function controller (PFC). This fact
can be used to send a break signal.
The DR value substitutes for the mark state until the PFC setting is made. The initial setting
should therefore be as an output port outputting 1.
To send a break signal during serial transmission, clear DR to 0, then set the TxD pin as an output
port with the PFC.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state.
Receive Error Flags and Transmit Operations (Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER3 to 0, or FER3 to 0) is set
to 1, even if the TE bit is set to 1. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
The SCI operates on a base clock with a frequency of 16, 8, or 4 times the transfer rate.
In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth, fourth, or second base clock
pulse. The timing is shown in figure 14.26.
Rev. 5.00 Sep 11, 2006 page 596 of 916
REJ09B0332-0500