SH7065 Datasheet, PDF (762/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
Table 19.4 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kB)
EB1 (4 kB)
EB2 (4 kB)
EB3 (4 kB)
EB4 (4 kB)
EB5 (4 kB)
EB6 (4 kB)
EB7 (4 kB)
EB8 (32 kB)
EB9 (64 kB)
EB10 (64 kB)
EB11 (64 kB)
Addresses
H'000000–H'000FFF
H'001000–H'001FFF
H'002000–H'002FFF
H'003000–H'003FFF
H'004000–H'004FFF
H'005000–H'005FFF
H'006000–H'006FFF
H'007000–H'007FFF
H'008000–H'00FFFF
H'010000–H'01FFFF
H'020000–H'02FFFF
H'030000–H'03FFFF
19.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 19.5. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Rev. 5.00 Sep 11, 2006 page 740 of 916
REJ09B0332-0500