SH7065 Datasheet, PDF (491/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

H'FFFF
TPDR
TGRUU
Td
TGRU
TGRUD
Section 11 Motor Management Timer (MMT)
2Td
TCNT
1/2 period
Td
(TPBR)
2Td
H'0000
2Td
Td
Figure 11.3 Example of TCNT Count Operation
Register Operation
In the operating modes, four buffer registers and ten compare registers are used.
The registers constantly compared with the TCNT counter are TGRU, TGRV, and TGRW. In
addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when it is when
counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when it is counting
down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU, and
TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the buffer
register for TGRWU, TGRW, and TGRWD is TBRW.
To change compare register data, the new data should be written to the corresponding buffer
register. The buffer registers can be read and written to at all times. Data written to TPBR and to
the buffer operation addresses for and TBRU to TBRW is transferred at the timing specified by
bits MD1 and MD0 in the timer mode register (TMDR). Data written to the free operation
addresses for TBRU to TBRW is transferred immediately.
After data transfer is completed, the relationship between the compare registers and buffer
registers is as follows.
Rev. 5.00 Sep 11, 2006 page 469 of 916
REJ09B0332-0500