SH7065 Datasheet, PDF (545/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 14 Serial Communication Interface (SCI)
14.2.2 Receive FIFO Data Register (SCFRDR)
Bit:
7
6
5
4
3
2
1
0
R/W: R
R
R
R
R
R
R
R
The receive FIFO data register (SCFRDR) is a 16-stage FIFO register (8 bits per stage) that stores
received serial data.
When the SCI has received one byte of serial data, it transfers the received data from SCRSR to
SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO data
register is full (16 data bytes).
SCFRDR is a read-only register, and cannot be written to.
If a read is performed when there is no receive data in the receive FIFO data register, an undefined
value will be returned. When the receive FIFO data register is full of receive data, subsequent
receive data is lost.
14.2.3 Transmit Shift Register (SCTSR)
Bit:
7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
The transmit shift register (SCTSR) is the register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from SCFTDR to SCTSR,
then sends the data to the TxD pin starting with the LSB (bit 0) or MSB (bit 7).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR
to SCTSR, and transmission started, automatically.
SCTSR cannot be read or written to directly.
Rev. 5.00 Sep 11, 2006 page 523 of 916
REJ09B0332-0500