SH7065 Datasheet, PDF (28/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 1 Overview
Item
Specifications
Compare-match
timer (CMT)
(2 channels)
• 16-bit free-running counter
• One compare register
• Interrupt request generated by compare-match
Watchdog timer • Can be switched between watchdog timer and interval timer function
(WDT) (1 channel) _{• Internal reset, external signal, or interrupt generated by count overflow}
Serial
communication
interface (SCI)
(3 channels)
For each channel:
• Selection of asynchronous or synchronous mode
• Simultaneous transmission/reception (full-duplex) capability
• Built-in dedicated baud rate generator
• Multiprocessor communication function
• Separate 16-stage FIFO registers for transmission and reception, enabling
continuous high-speed communication
I/O ports
A/D converter
D/A converter
On-chip memory
• Selection of MSB-first or LSB-first transfer
• Selection of base clock of 4/8/16 times the bit rate in asynchronous mode
• Built-in IrDA interface (conforming to IrDA 1.0)
• Total of 118 port pins: 110 input/output, 8 input
• Input/output voltage level for some ports can be set by I/O circuit power
supply PVCC
• 10 bits × 4 channels × 2 modules
• Conversion can be activated by external trigger
• 8 bits × 2 channels
• ROM: 256 kbytes
• X-RAM: 4 kbytes
• Y-RAM: 4 kbytes
Rev. 5.00 Sep 11, 2006 page 6 of 916
REJ09B0332-0500