SH7065 Datasheet, PDF (35/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 1 Overview
Type
Symbol
Direct memory DREQ0–
access
DREQ1
controller
(DMAC)
DRAK0–
DRAK1
DACK0–
DACK1
TEND0–
TEND1
Timer pulse
unit (TPU)
TCLKA–
TCLKD
TIOC0A–
TIOC0D
TIOC1A–
TIOC1B
TIOC2A–
TIOC2B
TIOC3A–
TIOC3D
TIOC4A–
TIOC4B
TIOC5A–
TIOC5B
I/O
Input
Name
DMA transfer
request
(channels 0, 1)
Function
Input pins for external requests for DMA
transfer.
Output
Output
Output
Input
I/O
I/O
I/O
I/O
I/O
I/O
DREQ request
acknowledg-
ment
(channels 0, 1)
DMA transfer
strobe
(channels 0, 1)
DMA transfer
end
(channels 0, 1)
TPU timer
clock input
TPU input
capture/output
compare
(channel 0)
TPU input
capture/output
compare
(channel 1)
TPU input
capture/output
compare
(channel 2)
TPU input
capture/output
compare
(channel 3)
TPU input
capture/output
compare
(channel 4)
TPU input
capture/output
compare
(channel 5)
These pins output the input sampling
acknowledgment for external requests
for DMA transfer.
These pins output a strobe to the
external I/O in external DMA transfer
requests.
These pins go low at the end of DMA
transfer.
TPU counter external clock Input pins.
Channel 0 input capture input/output
compare output/PWM output pins.
Channel 1 input capture input/output
compare output/PWM output pins.
Channel 2 input capture input/output
compare output/PWM output pins.
Channel 3 input capture input/output
compare output/PWM output pins.
Channel 4 input capture input/output
compare output/PWM output pins.
Channel 5 input capture input/output
compare output/PWM output pins.
Rev. 5.00 Sep 11, 2006 page 13 of 916
REJ09B0332-0500