SH7065 Datasheet, PDF (173/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
exited while BREQ input is still asserted, BACK output goes low and the bus-released state is
maintained. If software standby is exited while BREQ input is negated, BACK output goes
high and the chip returns to the normal state (in which the bus is not released).
2. Transition from normal state (BREQ input negated high) to software standby state
When a transition is made from the normal state to the software standby state, BACK output
goes to the Z (high-impedance) state, and the external bus goes to the high-impedance state,
i.e. the bus-released state. If this state is exited while BREQ input is negated, BACK output
returns to the high level. If BREQ input is in the asserted state when software standby is
exited, BACK is output high for 1.5 external clock (CKE) cycles, and then returns to the low
level, i.e. the bus-released state.
Table 4.15 State of Registers in Software Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Clock pulse generator (CPG)
Direct memory access controller
(DMAC)
Timer pulse unit (TPU)
Motor management timer (MMT)
Watchdog timer (WDT)
Serial communication interface (SCI)
A/D converter (A/D)
D/A converter (D/A)
Compare match timer (CMT)
Pin function controller (PFC)
I/O ports (I/O)
Power-down mode related modules
Initialized Registers
—
—
—
—
All registers
All registers
All registers
• OVF, WT/IT, and TME
bits in TCSR register
• RSTCSR register
All registers
All registers
All registers
All registers
—
—
—
Registers Retaining
Contents
All registers
All registers
All registers
All registers
—
—
—
• Bits CKS2 to CKS0 in
TCSR register
• TCNT registers
—
—
—
—
All registers
All registers
All registers
Rev. 5.00 Sep 11, 2006 page 151 of 916
REJ09B0332-0500