SH7065 Datasheet, PDF (512/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 11 Motor Management Timer (MMT)
Bit 8—Port Interrupt Enable (PIE): Enables or disables an interrupt request when 1 is set in any
of bits POE0F to POE3F in ICSR.
Bit 8: PIE
0
1
Description
Interrupt request disabled
Interrupt request enabled
(Initial value)
Bits 7 and 6—POE3 Mode 1 and 0 (POE3M1, POE3M0): These bits select the input mode of
the POE3 pin.
Bit 7: POE3M1
0
1
Bit 6: POE3M0
0
1
0
1
Description
Request accepted at falling edge of POE3 input
(Initial value)
POE3 input is sampled for low level 16 times every Pφ/8
clock, and request is accepted when all samples are low
level
POE3 input is sampled for low level 16 times every Pφ/16
clock, and request is accepted when all samples are low
level
POE3 input is sampled for low level 16 times every Pφ/128
clock, and request is accepted when all samples are low
level
Bits 5 and 4—POE2 Mode 1 and 0 (POE2M1, POE2M0): These bits select the input mode of
the POE2 pin.
Bit 5: POE2M1
0
1
Bit 4: POE2M0
0
1
0
1
Description
Request accepted at falling edge of POE2 input
(Initial value)
POE2 input is sampled for low level 16 times every Pφ/8
clock, and request is accepted when all samples are low
level
POE2 input is sampled for low level 16 times every Pφ/16
clock, and request is accepted when all samples are low
level
POE2 input is sampled for low level 16 times every Pφ/128
clock, and request is accepted when all samples are low
level
Rev. 5.00 Sep 11, 2006 page 490 of 916
REJ09B0332-0500