SH7065 Datasheet, PDF (692/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 17 Pin Function Controller (PFC)
Port D IO register H (PDIORH) is a 16-bit readable/writable register that selects the input/output
direction of pins in port D. Bits PD31IOR to PD16IOR correspond to pins
PD31/D31/RxD2/TIOC5A to PD16/D16/POE0. PDIORH is enabled when port D pins function as
general input/output pins (PD31 to PD16), SCI SCK pins, or TPU TIOC pins, or when PD23
functions as the MMT PCIO pin, and disabled otherwise.
When port D pins function as PD31 to PD16, SCI SCK pins, or TPU TIOC pins, or when PD23
functions as the MMT PCIO pin, a pin becomes an output when the corresponding bit in PDIORH
is set to 1, and an input when the bit is cleared to 0.
PDIORH is initialized to H'0000 by an external power-on reset, but is not initialized by a WDT
reset, in standby mode, or in sleep mode.
17.3.14 Port D IO Register L (PDIORL)
Bit: 15
14
13
12
11
10
9
8
PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port D IO register L (PDIORL) is a 16-bit readable/writable register that selects the input/output
direction of pins in port D. Bits PD15IOR to PD0IOR correspond to pins PD15/D15/TIOC5B to
PD0/D0. PDIORL is enabled when port D pins function as general input/output pins (PD15 to
PD0) or TPU TIOC pins, and disabled otherwise.
When port D pins function as PD15 to PD0 or TPU TIOC pins, a pin becomes an output when the
corresponding bit in PDIORL is set to 1, and an input when the bit is cleared to 0.
PDIORL is initialized to H'0000 by an external power-on reset, but is not initialized by a WDT
reset, in standby mode, or in sleep mode.
Rev. 5.00 Sep 11, 2006 page 670 of 916
REJ09B0332-0500