SH7065 Datasheet, PDF (746/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 18 I/O Ports (I/O)
18.10.2 Port I Data Register (PIDR)
Bit: 7
6
5
4
3
2
PI7DR PI6DR PI5DR PI4DR PI3DR PI2DR
Initial value:
*
*
*
*
*
*
R/W: R
R
R
R
R
R
Note: * Initial value depends on the pin state when a read is performed.
1
PI1DR
*
R
0
PI0DR
*
R
The port I data register (PIDR) is an 8-bit read-only register that stores port I data. Bits PI7DR to
PI0DR correspond to pins PI7/AN7 to PI0/An0.
Writes to these bits are ignored, and do not affect the pin states. When these bits are read the pin
state, not the register value, is returned directly. However, 1 will be returned while A/D converter
analog input is being sampled. Table 18.18 summarizes port I data register read/write operations.
PIDR is not initialized by a power-on or WDT reset, or in standby mode or sleep mode. (The bits
always reflect the pin states.)
Table 18.18 Port I Data Register (PIDR) Read/Write Operations
Pin Input/Output
Input
Legend:
ANn: Analog input
Pin Function
General input
ANn
Read
Pin state is read
1 is read
Write
Ignored (does not affect pin state)
Ignored (does not affect pin state)
Rev. 5.00 Sep 11, 2006 page 724 of 916
REJ09B0332-0500