SH7065 Datasheet, PDF (466/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figure 10.45 shows the timing of status flag clearing
by the CPU, and figure 10.46 shows the timing of status flag clearing by the DMAC.
TSR write cycle
T1 T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.45 Timing of Status Flag Clearing by CPU
DMAC
read cycle
T1 T2
DMAC
write cycle
T1 T2
Pφ
Address
Source address Destination address
Status flag
Interrupt
request signal
Figure 10.46 Timing of Status Flag Clearing by DMAC Activation
Rev. 5.00 Sep 11, 2006 page 444 of 916
REJ09B0332-0500