SH7065 Datasheet, PDF (205/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 6 Interrupt Controller (INTC)
The priority of on-chip peripheral module interrupts can be set to any level from 0 to 15 for each
module using interrupt priority registers E to L (IPRE to IPRL). The “Priority within IPR Setting”
column in table 6.6 shows the relative priority of interrupts sharing the same IPR field. This
priority order cannot be changed. In a power-on reset, IRQ interrupts and on-chip peripheral
module interrupts are set to priority level 0. If two or more interrupt sources assigned the same
priority level occur simultaneously, they are handled according to the default priority order shown
in tables 6.4 to 6.6.
Table 6.4 IRQ Mode Interrupt Exception Vectors and Priority Order
Interrupt
Source
NMI
User break
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt
Priority
(Initial Value)
16
15
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
IPR
(Bit Numbers)
—
—
IPRA (15–12)
IPRA (11–8)
IPRA (7–4)
IPRA (3–0)
IPRB (15–12)
IPRB (11–8)
IPRB (7–4)
IPRB (3–0)
Vector
Number
12
13
64
65
66
67
80
81
82
83
Vector
Vector
Table Offset
H'0000 0030
H'0000 0034
H'0000 0100
H'0000 0104
H'0000 0108
H'0000 010C
H'0000 0140
H'0000 0144
H'0000 0148
H'0000 014C
Default
Priority
High
Low
Rev. 5.00 Sep 11, 2006 page 183 of 916
REJ09B0332-0500