SH7065 Datasheet, PDF (26/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 1 Overview
Item
Interrupt
controller (INTC)
User break
controller (UBC)
Bus state
controller (BSC)
Specifications
• Nine external interrupt pins (NMI, IRQ0 to IRQ7)
15 external interrupt sources (encoded input) can also be selected for pins
IRQ0 to IRQ3
• 16 programmable priority levels
• NMI noise canceler function
• Interrupt acceptance can be reported externally (IRQOUT pin)
• Requests an interrupt when the CPU or DMAC generates a bus cycle with
specific set conditions
• Simplifies configuration of an on-chip debugger
• Supports external expansion memory access
 32-bit external data bus
• Address space divided into six areas (four areas in SRAM space, two
areas in DRAM space), with the following parameters settable for each
area:
 Bus size (8/16/32 bits)
 Number of wait cycles
 SRAM, DRAM, and EDO DRAM easily connectable by space type
setting
 Output of RAS and CAS signals for DRAM and EDO DRAM
 Addressing multiplexing supported internally, allowing direct connection
of DRAM and EDO DRAM
• DRAM and EDO DRAM burst access functions
 DRAM and EDO DRAM fast access mode supported
• DRAM and EDO DRAM refresh functions
 Programmable refresh interval
 CAS-before-RAS refreshing and self-refreshing supported
 Up to eight consecutive CAS-before-RAS refreshes possible
• Wait cycles can be inserted using an external WAIT signal
• Can access I/O devices that use address/data multiplexing
• Big-endian or little-endian mode can be set independently for each area
Rev. 5.00 Sep 11, 2006 page 4 of 916
REJ09B0332-0500