SH7065 Datasheet, PDF (472/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 10.52 shows the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal data
bus
M
Figure 10.52 Contention between TGR Read and Input Capture
Rev. 5.00 Sep 11, 2006 page 450 of 916
REJ09B0332-0500