SH7065 Datasheet, PDF (266/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Bit 9—Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression
of an interrupt request when the OVF flag is set to 1 in RTCSR.
Bit 9: OVIE
0
1
Description
Interrupts initiated by OVF are disabled
Interrupts initiated by OVF are enabled
(Initial value)
Bits 8 and 7—Refresh Count Overflow Limit Select (LMTS1, LMTS0): These bits specify the
count limit to be compared with the refresh count indicated by the refresh count register (RFCR).
If the RFCR register value exceeds the value specified by the LMTS bits, the OVF flag is set to 1.
Bit 8: LMTS1
0
1
Bit 7: LMTS0
0
1
0
1
Description
Refresh count limit is 4096
Refresh count limit is 2048
Refresh count limit is 1024
Refresh count limit is 512
(Initial value)
Bits 6 to 4—Refresh Request Number Select (BREF2 to BREF0): These bits specify the
number of consecutive refresh requests requested by a single compare match. The number of
CAS-before-RAS refreshes specified by these bits are performed consecutively.
Bit 6:
BREF2
0
1
Bit 5:
BREF1
0
1
0
1
Bit 4:
BREF0
0
1
0
1
0
1
0
1
Description
1 CAS-before-RAS refresh is performed (Initial value)
2 consecutive CAS-before-RAS refreshes are performed
3 consecutive CAS-before-RAS refreshes are performed
4 consecutive CAS-before-RAS refreshes are performed
5 consecutive CAS-before-RAS refreshes are performed
6 consecutive CAS-before-RAS refreshes are performed
7 consecutive CAS-before-RAS refreshes are performed
8 consecutive CAS-before-RAS refreshes are performed
Bits 3 to 1—Refresh RAS Assertion Interval Specification (TRAS2 to TRAS0): These bits
specify the refresh interval of the DRAM connected to areas 4 and 5. With DRAM, this is the RAS
assertion interval in CAS-before-RAS refreshing.
Rev. 5.00 Sep 11, 2006 page 244 of 916
REJ09B0332-0500