SH7065 Datasheet, PDF (181/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator (CPG) and Power-Down Modes
Table 4.19 MCLK Bits and Corresponding On-Chip Peripheral Modules
Bit^*1
Description
Maximum Operating
Frequency
MCLK191–190
CPU^*2
60 MHz
MCLK181–180
—
—
MCLK171–170
—
—
MCLK161–160
—
—
MCLK152–150
Serial communication interface (SCI) channel 0
30 MHz
MCLK142–140
Serial communication interface (SCI) channel 1
30 MHz
MCLK132–130
Serial communication interface (SCI) channel 2
30 MHz
MCLK122–120
—
—
MCLK112–110
Compare match timer (CMT)
30 MHz
MCLK102–100
—
—
MCLK092–090
Motor management timer (MMT)
30 MHz
MCLK082–080
Port output enable (POE)
30 MHz
MCLK072–070
Timer pulse unit (TPU)
30 MHz
MCLK062–060
A/D converter (A/D)
20 MHz
(clock select CKS = 1)
30 MHz
(clock select CKS = 0)
MCLK052–050
D/A converter (D/A)
30 MHz
MCLK042–040
—
—
MCLK032–030
—
—
MCLK022–020
—
—
MCLK012–010
—
—
MCLK002–000
—
—
Notes: 1. Bits to which a module is not assigned must be written with their initial value.
2. Including the DMAC, ROM, X-RAM, Y-RAM, UBC, and WDT.
Rev. 5.00 Sep 11, 2006 page 159 of 916
REJ09B0332-0500