SH7065 Datasheet, PDF (760/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 19 256 kB Flash Memory (F-ZTAT)
19.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is an 8-bit register used to monitor enabling or disabling of flash memory program/erase
protection (error protection).
FLMCR2 is initialized by a reset and in hardware standby mode. In the on-chip ROM disabled
modes (MCU modes 2, 3, and 4), a read will return H'00, and writes are invalid.
Note: FLMCR2 is a read-only register, and should not be written to.
Bit: 7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7: FLER
0
1
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
(Initial value)
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.8.3, Error Protection
Bits 6 to 0—Reserved: These bits are always read as 0.
Rev. 5.00 Sep 11, 2006 page 738 of 916
REJ09B0332-0500