SH7065 Datasheet, PDF (383/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 9 Direct Memory Access Controller (DMAC)
6. When activating the DMAC, make the CHCR setting as the final step. The DMAC may not
operate normally if any other register setting is made last.
7. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to
DMATCR even when executing the maximum number of transfers on the same channel. The
DMAC may not operate normally if this is not done.
8. When using the round robin method to determine the priority order, more than one channel
must be specified, and consecutive channel numbers must be specified (e.g. CH1, CH2, CH3).
Operation cannot be guaranteed if non-consecutive channel numbers are specified. To change
the specified channel, change the DMA operation register (DMAOR) setting when the channel
priority order is the initial priority order.
9. When falling edge detection is used for external requests, keep the external request pin high
when making DMAC settings.
10. When using the DMAC in single address mode, set an external address as the address. The
DMAC may not operate normally if an internal address is set.
11. On-chip ROM space cannot be accessed.
12. The same internal request cannot be set for more than one channel. If it is, the request will only
be valid for the channel with the highest default priority.
13. When a transfer request is accepted from an on-chip peripheral module, the relevant interrupt
request signal is masked and not input to the INTC. For details of the masking conditions, see
section 6, Interrupt Controller (INTC).
14. The DMAC internal registers cannot be accessed while the DMAC is operating. However, it is
possible to perform access to DMAOR and CHCRn, and change the DME bit in DMAOR and
the TE and DE bits in CHCRn to control DMAC operation. If any other bit in DMAOR or
CHCRn is changed, the change of setting may not be reflected in DMA transfer following the
change.
15. When performing chain transfer initiated by an on-chip module, the DS bit in CHCRn must be
set to 1.
16. When chain transfer is disabled by means of the CHNE bit in CHCRn, either clear CHNCNTn
to 0 or set the TES bit to 1 in CHCRn.
17. A transfer request should not be made until the DMAC register settings are completed
(figure 9.2).
Rev. 5.00 Sep 11, 2006 page 361 of 916
REJ09B0332-0500