SH7065 Datasheet, PDF (197/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 5 Exception Handling
5.7 Stack Status after Exception Handling
Table 5.10 shows the stack after completion of exception handling.
Table 5.10 Stack Status after Exception Handling
Type
Address error
Stack Status
SP
Address of instruction
following executed instruction
SR
32 bits
32 bits
TRAP instruction
SP
Address of instruction
following TRAPA instruction
SR
32 bits
32 bits
General illegal instruction
SP
Start address of illegal
instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
following executed instruction
32 bits
SR
32 bits
Slot illegal instruction
SP
Jump destination address
of delayed branch instruction
SR
32 bits
32 bits
Rev. 5.00 Sep 11, 2006 page 175 of 916
REJ09B0332-0500