SH7065 Datasheet, PDF (304/941 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Section 8 Bus State Controller (BSC)
Mφ
CKE
RTCNT input
clock
RTCNT value
N
0
RTCOR value
N
CMF
CMI
Refresh request
Figure 8.28 Timing of CMF Bit Setting (when M0: CKE = 1:1/2)
Figure 8.29 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by the TRAS bits in RTCSR.
The specification of the RAS precharge time in the refresh cycle is determined by the setting of
the TPC bits in DCR1.
CAS-before-RAS refreshing is performed in normal operation, in sleep mode.
Rev. 5.00 Sep 11, 2006 page 282 of 916
REJ09B0332-0500